Multilevel wiring and interconnect formation on semiconductor substrates play a significant role in determining overall semiconductor device operating speed, device yield and reliability. Reliance on the reliability of multilevel wiring and interconnects has also increased with the trend towards increased device integration in highly integrated circuits. Methods of forming multilayered wiring lines on semiconductor substrates typically include planarization steps to increase resolution and depth-of-focus during photolithography processing steps. In particular, conventional planarization steps which include the use of spin-on-glass (SOG) passivation layers are relatively simple and economical and are therefore widely used in methods of forming multilayered wiring lines.
Planarization steps using spin-on-glass passivation layers typically include a baking step which is performed at temperatures in a range between about 150 and 400.degree. C. The baking step is typically performed to dry off solvents and moisture from within the spin-on-glass passivation layer. Unfortunately, during the baking step, the spin-on-glass passivation layer may shrink and develop tensile stresses therein. In particular, when the spin-on-glass passivation layer has a thickness greater than about 3,000 .ANG., the magnitude of the tensile stresses may be sufficient to cause fine cracks in the spin-on-glass layer. To inhibit the formation of such fine cracks, a compound containing an organic group such as a methyl group (CH.sub.3.sup.-) or a phenyl group (C.sub.6 H.sub.5.sup.-) is typically added to the spin-on-glass passivation layer. Spin-on-glass passivation layers containing such organic groups are typically referred to as organic SOG. Prior to the use of organic SOG passivation layers, SOG passivation layers free of organic groups (hereinafter referred to as inorganic SOG passivation layers) were used because of the volatility and difficulty in retaining the organic compounds in the SOG passivation layers. However, many of these problems have been overcome and now organic SOG passivation layers are widely used in planarization technologies.
Referring now to FIGS. 1-4, a conventional method of interconnecting electrically conductive lines at different wiring levels will be described. In particular, FIG. 1 illustrates the steps of forming an underlying layer 20, a first lower conductive layer pattern 30a, a second lower conductive layer pattern 30b, a first interlayer dielectric layer 40 and an organic SOG passivation layer 50. Here, the lower conductive wiring line or layer is formed on the underlying layer 20 and the underlying layer 20 is formed on a semiconductor substrate (not shown) and has an uneven surface profile with upper and lower regions. The upper and lower regions will be referred to as first area "H" and second area "L", respectively.
The lower conductive layer patterns are formed on predetermined areas of the underlying layer 20 by patterning a lower conductive layer (e.g., metallization, polysilicon) until the underlying layer 20 is exposed. Here, a first lower conductive layer pattern 30a is formed on the first area H and a second lower conductive layer pattern 30b is formed on the second area L. Subsequently, a blanket first interlayer dielectric layer 40 (e.g., SiO.sub.2) is formed on the overall surface of the substrate having the first and second lower conductive layer patterns 30a and 30b formed thereon. As illustrated, the upper surface of the first interlayer dielectric layer 40 is uneven because of the step heights of the first and second lower conductive layer patterns 30a and 30b and the underlying layer 20. An organic SOG layer 50 is then formed on the overall surface of the substrate having the first interlayer dielectric layer 40 formed thereon. The organic SOG layer 50 acts as a planarization layer to reduce the unevenness of the surface topology of the first interlayer dielectric layer 40.
Referring now to FIG. 2, a step of forming a modified organic SOG layer 50a will be described. In particular, a modified organic SOG layer 50a is formed by etching back the overall surface of the organic SOG layer 50 to a predetermined depth until an upper surface of the first interlayer dielectric layer 40 (extending opposite an upper surface of the first lower conductive layer pattern 30a) is exposed. Here, the step of etching back the organic SOG layer 50 is performed to provide an improved planarized surface and to reduce the aspect ratio of a subsequently formed via extending opposite an upper surface of the second lower conductive layer pattern 30b. Since the overall surface of the organic SOG layer 50 is etched back until the first interlayer dielectric layer 40 is exposed, there exists essentially no modified organic SOG layer 50a extending opposite an upper surface of the first lower conductive layer pattern 30a. A carbon fluoride gas such as CF.sub.4 or C.sub.2 F.sub.6 is preferably used to perform the etch back steps. Here, a gas mixture further containing an inert gas such as argon (Ar) is used for producing sputtering effects as a purely chemical reaction does not allow for a smooth etch-back process. After the etch-back step has been performed, first material layers 55 are left as organic residues on the modified organic SOG layer 50a because the Si and O components of the organic SOG layer 50 evaporate away in the form of SiF.sub.4 and CO.sub.2, while the organic components of the SOG layer 50 are left behind as residues.
Referring now to FIG. 3, the steps of forming a first dielectric layer pattern 40a, an organic SOG layer pattern 50b, and a second dielectric layer pattern 60a will be described. In particular, a second interlayer dielectric layer is formed on the overall surface of the substrate having the modified organic SOG layer 50a formed thereon. Here, the adhesiveness of the second interlayer dielectric layer to the modified organic SOG layer 50a may become severely deteriorated because the first material residues 55 intervene locally between the modified organic SOG layer 50a and the second interlayer dielectric layer. The second interlayer dielectric layer pattern 60a, the organic SOG layer pattern 50b, and the first dielectric layer pattern 40a are then formed to have a first via hole V1 and a second via hole V2 therein by anisotropically etching the modified organic SOG layer 50a and the first interlayer dielectric layer 40 on the first lower conductive layer pattern 30a, and by anisotropically etching the second interlayer dielectric layer, the modified organic SOG layer 50a, and the first interlayer dielectric layer 40 on the second lower conductive layer pattern 30b, using a mixed gas containing a carbon fluoride gas such as CF.sub.4 or C.sub.2 F.sub.6 gas and an inert gas such as argon for bringing about sputtering effects. These first and second via holes expose the first and second lower conductive layer patterns 30a and 30b, respectively.
Because the modified organic SOG layer 50a is formed thicker on the second lower conductive layer pattern 30b, a relatively large amount of organic SOG is typically etched to form the second via hole V2. Therefore, for the same reason that organic residues are left on the modified organic SOG layer 50a of FIG. 2, additional organic residues 65 are deposited on the bottom of the second via hole V2. In contrast, organic residues are not formed on the bottom of the first via hole V1 because all of the modified organic SOG layer 50a was removed from the portion of the first interlayer dielectric layer 40 extending opposite the first lower conductive layer pattern 30a, prior to the etching step.
Referring now to FIG. 4, an upper conductive layer 70 is formed to fill the first and second via holes V1 and V2 on the overall surface of the substrate having the second interlayer dielectric layer pattern 60a, the organic SOG layer pattern 50b, and the first interlayer dielectric layer pattern 40a formed thereon. However, the existence of the second material layer 65 on the bottom of the second via hole V2 may preclude the formation of a reliable ohmic contact between the upper conductive layer 70 and the second lower conductive layer pattern 30b. In addition, the adhesiveness between the organic SOG layer pattern 50b and the second interlayer dielectric layer pattern 60a is weakened due to the first material residues 55, and thus the second interlayer dielectric layer pattern 60a is susceptible to flaking.
Thus, notwithstanding the above described methods, there continues to be a need for improved methods of interconnecting electrically conductive lines on semiconductor substrates.